1. Field of Invention
The present invention relates to semiconductor devices, and more particularly to a semiconductor device, an electro-optical device, and an electronic apparatus in which degradation in performance over time can be reduced, minimized or prevented.
2. Description of Related Art
FIGS. 1(a)–1(c) show a thin-film transistor as an example of a conventional semiconductor device. FIG. 1(a) is a plan view of a conventional polycrystalline-silicon thin-film transistor, FIG. 1(b) is a sectional view taken along plane b—b in the plan view of FIG. 1(a), and FIG. 1(c) is a sectional view taken along the plane c—c in the plan view of FIG. 1(a). As shown in FIGS. 1(a)–1(c), the polycrystalline-silicon thin-film transistor generally has a top gate structure, as disclosed in Liquid Crystal Display Technology written and edited by Shoichi Matsumoto, published by Sangyo Tosho.
FIGS. 2(a)–2(c) show a manufacturing process of a typical polycrystalline-silicon thin-film transistor. First, an amorphous silicon layer is formed on a glass substrate 51 by PECVD using SiH4 or LPCVD using Si2H6, as shown in FIG. 2(a). The amorphous silicon layer is recrystallized by radiating with, for example, an excimer laser or by solid-phase growth to form a polycrystalline silicon layer 52. Next, as shown in FIG. 2(b), the polycrystalline silicon layer 52 is patterned so as to have an island shape, and then is provided with a gate insulating film 53 thereon. Subsequently, a gate electrode 54 is formed by deposition and patterning. Next, as shown in FIG. 2(c), a dopant, such as phosphorous or boron, is implanted into the polycrystalline silicon layer 52 by self-aligning using the gate electrode 54. Subsequently, the polycrystalline silicon layer 52 is activated, and thus source/drain regions 55, which have a CMOS structure, are formed. Following the formation of an interlayer insulating film 56 and a contact hole, source/drain electrodes 57 are formed by deposition and patterning.
Conventional semiconductor devices, such as MOS elements, have had a problem in that their performance deteriorates over time while the devices are operated for a long time. It is thought that this degradation over time is caused by an electric field concentrated at, for example, ends of a semiconductor film serving as an active layer, or at an interface between the semiconductor film and an insulating layer. The degradation over time arising from this cause is significant in some semiconductor devices, such as thin-film transistors, which include a thin semiconductor film serving as an active layer on the insulating layer.
In the thin-film transistor, since an electric field is concentrated at the ends of the semiconductor film, the electric field strength increases. In addition, since the thickness of the semiconductor film is small, the carrier concentration is liable to increase.
FIGS. 3(a) and 3(b) show results of distribution analyses, by device simulation, of the electric field strength and the carrier concentration of the polycrystalline silicon thin-film transistors. The electric field strength distribution in FIG. 3(a) shows that a substantially central area of the semiconductor film had an electric field strength of 4.5×105 V/cm, and that a far end of the semiconductor film had a high electric field strength of 6.6×105 V/cm. Also, FIG. 3(b) shows that the substantially central area of the semiconductor film had a carrier concentration of 2.7×1017 cm−3, and that the far end of the semiconductor film had a carrier concentration of 1.6×1020 cm−3. 